#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments

NET "IN1"  LOC = "P38" | IOSTANDARD = LVCMOS33  | PULLUP ;

NET "IN2"  LOC = "P37" | IOSTANDARD = LVCMOS33  | PULLUP ;

NET "OUT1"  LOC = "P28" | SLEW = SLOW  | IOSTANDARD = LVCMOS33  | FLOAT ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

NET "XTALIN"  LOC = "P12" | IOSTANDARD = LVTTL ; 

NET "XTALOUT1"  LOC = "P18" | SLEW = FAST  | IOSTANDARD = LVTTL ; 

NET "XTALOUT2"  LOC = "P14" | SLEW = FAST  | IOSTANDARD = LVTTL ;

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library UNISIM;

use UNISIM.Vcomponents.ALL;

entity top is
   port ( XTALIN   : in    std_logic; 
          XTALOUT1 : out   std_logic; 
          XTALOUT2 : out   std_logic);

end top;

architecture BEHAVIORAL of top is
   attribute BOX_TYPE   : string ;
   signal XLXN_25  : std_logic;
   signal XLXN_58  : std_logic;
   signal XLXN_61  : std_logic;
   component IBUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
   
   component OBUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";

begin
   XLXI_29 : IBUF
      port map (I=>XTALIN,
                O=>XLXN_25);
   
   XLXI_31 : OBUF
      port map (I=>XLXN_61,
                O=>XTALOUT1);
   
   XLXI_32 : INV
      port map (I=>XLXN_25,
                O=>XLXN_61);
   
   XLXI_33 : INV
      port map (I=>XLXN_61,
                O=>XLXN_58);
   
   XLXI_59 : OBUF
      port map (I=>XLXN_58,
                O=>XTALOUT2);

end BEHAVIORAL;

Device Used: XC2C64A-7-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************
Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
2  /64  (  3%) 2   /224  (  1%) 2   /160  (  1%) 0  /64  (  0%) 3  /33  (  9%)

** Function Block Resources **
Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB2       0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB3       1/16      1/40     1/56     1/ 9    0/1      0/1      0/1      0/1
FB4       1/16      1/40     1/56     1/ 7    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total     2/64      2/160    2/224    2/33    0/4      0/4      0/4      0/4 

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

** 2 Outputs **
Signal              Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
XTALOUT1            1     1     2    FB3_15  18    I/O       O       LVTTL              FAST         
XTALOUT2            1     1     1    FB4_14  14    I/O       O       LVTTL              FAST         

** 1 Inputs **
Signal              Bank Loc     Pin   Pin       Pin     I/O      I/O
Name                             No.   Type      Use     STD      Style
XTALIN              1    FB4_11  12    I/O       I       LVTTL    KPR

******************************  Device Pin Out *****************************
Device : XC2C64A-7-VQ44
   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC2C64A-7-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  

Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 KPR                           
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCCIO-3.3                     
  5 KPR                              27 KPR                           
  6 KPR                              28 KPR                           
  7 VCCIO-3.3                        29 KPR                           
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 KPR                           
 11 TCK                              33 KPR                           
 12 XTALIN                           34 KPR                           
 13 KPR                              35 VCCAUX                        
 14 XTALOUT2                         36 KPR                           
 15 VCC                              37 KPR                           
 16 KPR                              38 KPR                           
 17 GND                              39 KPR                           
 18 XTALOUT1                         40 KPR                           
 19 KPR                              41 KPR                           
 20 KPR                              42 KPR                           
 21 KPR                              43 KPR                           
 22 KPR                              44 KPR                           

Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
 
entity COMPM8_MXILINX_top is
   port ( A  : in    std_logic_vector (7 downto 0); 
          B  : in    std_logic_vector (7 downto 0); 
          GT : out   std_logic; 
          LT : out   std_logic);
end COMPM8_MXILINX_top;
 
architecture BEHAVIORAL of COMPM8_MXILINX_top is
   attribute BOX_TYPE   : string ;
   signal EQ_1  : std_logic;
   signal EQ_3  : std_logic;
   signal EQ_5  : std_logic;
   signal EQ_7  : std_logic;
   signal EQ2_3 : std_logic;
   signal EQ4_5 : std_logic;
   signal EQ6_7 : std_logic;
   signal GE0_1 : std_logic;
   signal GE2_3 : std_logic;
   signal GE4_5 : std_logic;
   signal GE6_7 : std_logic;
   signal GTA   : std_logic;
   signal GTB   : std_logic;
   signal GTC   : std_logic;
   signal GTD   : std_logic;
   signal GT_1  : std_logic;
   signal GT_3  : std_logic;
   signal GT_5  : std_logic;
   signal GT_7  : std_logic;
   signal GT0_1 : std_logic;
   signal GT2_3 : std_logic;
   signal GT4_5 : std_logic;
   signal LE0_1 : std_logic;
   signal LE2_3 : std_logic;
   signal LE4_5 : std_logic;
   signal LE6_7 : std_logic;
   signal LTA   : std_logic;
   signal LTB   : std_logic;
   signal LTC   : std_logic;
   signal LTD   : std_logic;
   signal LT_1  : std_logic;
   signal LT_3  : std_logic;
   signal LT_5  : std_logic;
   signal LT_7  : std_logic;
   signal LT0_1 : std_logic;
   signal LT2_3 : std_logic;
   signal LT4_5 : std_logic;
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
   component OR4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
   
   component NOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of NOR2 : component is "BLACK_BOX";
   
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   component AND3B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
   
   component XNOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XNOR2 : component is "BLACK_BOX";
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
   
begin
   I_36_1 : AND2B1
      port map (I0=>A(7),
                I1=>B(7),
                O=>LT_7);
   
   I_36_3 : OR4
      port map (I0=>LTD,
                I1=>LTC,
                I2=>LTB,
                I3=>LTA,
                O=>LT);
   
   I_36_4 : NOR2
      port map (I0=>GT4_5,
                I1=>LT4_5,
                O=>EQ4_5);
   
   I_36_5 : AND3
      port map (I0=>EQ6_7,
                I1=>EQ4_5,
                I2=>LT2_3,
                O=>LTB);
   
   I_36_6 : OR2
      port map (I0=>LT_3,
                I1=>LE2_3,
                O=>LT2_3);
   
   I_36_7 : OR2
      port map (I0=>GT_3,
                I1=>GE2_3,
                O=>GT2_3);
   
   I_36_8 : OR2
      port map (I0=>GT_1,
                I1=>GE0_1,
                O=>GT0_1);
   
   I_36_9 : AND3B1
      port map (I0=>A(0),
                I1=>EQ_1,
                I2=>B(0),
                O=>LE0_1);
   
   I_36_10 : AND3B1
      port map (I0=>B(0),
                I1=>EQ_1,
                I2=>A(0),
                O=>GE0_1);
   
   I_36_11 : AND3B1
      port map (I0=>A(2),
                I1=>EQ_3,
                I2=>B(2),
                O=>LE2_3);
   
   I_36_12 : AND3B1
      port map (I0=>B(2),
                I1=>EQ_3,
                I2=>A(2),
                O=>GE2_3);
   
   I_36_13 : XNOR2
      port map (I0=>A(1),
                I1=>B(1),
                O=>EQ_1);
   
   I_36_14 : AND2B1
      port map (I0=>B(1),
                I1=>A(1),
                O=>GT_1);
   
   I_36_15 : XNOR2
      port map (I0=>A(3),
                I1=>B(3),
                O=>EQ_3);
   
   I_36_16 : AND2B1
      port map (I0=>A(1),
                I1=>B(1),
                O=>LT_1);
   
   I_36_17 : AND2B1
      port map (I0=>B(3),
                I1=>A(3),
                O=>GT_3);
   
   I_36_18 : OR2
      port map (I0=>LT_1,
                I1=>LE0_1,
                O=>LT0_1);
   
   I_36_19 : AND2B1
      port map (I0=>A(3),
                I1=>B(3),
                O=>LT_3);
   
   I_36_20 : AND2
      port map (I0=>GT4_5,
                I1=>EQ6_7,
                O=>GTC);
   
   I_36_21 : AND2
      port map (I0=>EQ6_7,
                I1=>LT4_5,
                O=>LTC);
   
   I_36_22 : NOR2
      port map (I0=>GTD,
                I1=>LTD,
                O=>EQ6_7);
   
   I_36_23 : OR2
      port map (I0=>LT_5,
                I1=>LE4_5,
                O=>LT4_5);
   
   I_36_24 : AND2B1
      port map (I0=>B(7),
                I1=>A(7),
                O=>GT_7);
   
   I_36_25 : AND2B1
      port map (I0=>A(5),
                I1=>B(5),
                O=>LT_5);
   
   I_36_26 : XNOR2
      port map (I0=>A(7),
                I1=>B(7),
                O=>EQ_7);
   
   I_36_27 : AND2B1
      port map (I0=>B(5),
                I1=>A(5),
                O=>GT_5);
   
   I_36_28 : XNOR2
      port map (I0=>A(5),
                I1=>B(5),
                O=>EQ_5);
   
   I_36_29 : AND3B1
      port map (I0=>B(6),
                I1=>EQ_7,
                I2=>A(6),
                O=>GE6_7);
   
   I_36_30 : AND3B1
      port map (I0=>A(6),
                I1=>EQ_7,
                I2=>B(6),
                O=>LE6_7);
   
   I_36_31 : AND3B1
      port map (I0=>B(4),
                I1=>EQ_5,
                I2=>A(4),
                O=>GE4_5);
   
   I_36_32 : AND3B1
      port map (I0=>A(4),
                I1=>EQ_5,
                I2=>B(4),
                O=>LE4_5);
   
   I_36_33 : OR2
      port map (I0=>GT_5,
                I1=>GE4_5,
                O=>GT4_5);
   
   I_36_34 : OR2
      port map (I0=>GT_7,
                I1=>GE6_7,
                O=>GTD);
   
   I_36_35 : OR2
      port map (I0=>LT_7,
                I1=>LE6_7,
                O=>LTD);
   
   I_36_36 : AND4
      port map (I0=>EQ6_7,
                I1=>EQ4_5,
                I2=>EQ2_3,
                I3=>LT0_1,
                O=>LTA);
   
   I_36_37 : AND4
      port map (I0=>GT0_1,
                I1=>EQ2_3,
                I2=>EQ4_5,
                I3=>EQ6_7,
                O=>GTA);
   
   I_36_38 : AND3
      port map (I0=>GT2_3,
                I1=>EQ4_5,
                I2=>EQ6_7,
                O=>GTB);
   
   I_36_39 : NOR2
      port map (I0=>GT2_3,
                I1=>LT2_3,
                O=>EQ2_3);
   
   I_36_40 : OR4
      port map (I0=>GTD,
                I1=>GTC,
                I2=>GTB,
                I3=>GTA,
                O=>GT);
end BEHAVIORAL;
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
 
entity CJD8CE_MXILINX_top is
   port ( C   : in    std_logic; 
          CE  : in    std_logic; 
          CLR : in    std_logic; 
          Q   : out   std_logic_vector (7 downto 0));
end CJD8CE_MXILINX_top;
 
architecture BEHAVIORAL of CJD8CE_MXILINX_top is
   attribute BOX_TYPE   : string ;
   signal Q7B     : std_logic;
   signal Q_DUMMY : std_logic_vector (7 downto 0);
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component FDDCE
      generic( INIT : bit :=  '0');
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute BOX_TYPE of FDDCE : component is "BLACK_BOX";
   
begin
   Q(7 downto 0) <= Q_DUMMY(7 downto 0);
   I_36_61 : INV
      port map (I=>Q_DUMMY(7),
                O=>Q7B);
   
   XLXI_1 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(2),
                Q=>Q_DUMMY(3));
   
   XLXI_2 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(1),
                Q=>Q_DUMMY(2));
   
   XLXI_3 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(0),
                Q=>Q_DUMMY(1));
   
   XLXI_4 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q7B,
                Q=>Q_DUMMY(0));
   
   XLXI_5 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(3),
                Q=>Q_DUMMY(4));
   
   XLXI_6 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(4),
                Q=>Q_DUMMY(5));
   
   XLXI_7 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(5),
                Q=>Q_DUMMY(6));
   
   XLXI_8 : FDDCE
      port map (C=>C,
                CE=>CE,
                CLR=>CLR,
                D=>Q_DUMMY(6),
                Q=>Q_DUMMY(7));   
end BEHAVIORAL;
 
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
 
entity top is
   port ( D0       : in    std_logic; 
          D1       : in    std_logic; 
          D2       : in    std_logic; 
          D3       : in    std_logic; 
          D4       : in    std_logic; 
          D5       : in    std_logic; 
          XTALIN   : in    std_logic; 
          PWMN     : out   std_logic; 
          PWMP     : out   std_logic; 
          XTALOUT1 : out   std_logic; 
          XTALOUT2 : out   std_logic);
end top;
 
architecture BEHAVIORAL of top is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal A        : std_logic_vector (7 downto 0);
   signal B        : std_logic_vector (7 downto 0);
   signal Q        : std_logic_vector (7 downto 0);
   signal XLXN_25  : std_logic;
   signal XLXN_58  : std_logic;
   signal XLXN_61  : std_logic;
   signal XLXN_176 : std_logic;
   signal XLXN_177 : std_logic;
   signal XLXN_179 : std_logic;
   signal XLXN_180 : std_logic;
   component IBUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of IBUF : component is "BLACK_BOX";
   
   component OBUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of OBUF : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component CJD8CE_MXILINX_top
      port ( C   : in    std_logic; 
             CE  : in    std_logic; 
             CLR : in    std_logic; 
             Q   : out   std_logic_vector (7 downto 0));
   end component;
   
   component PULLUP
      port ( O : out   std_logic);
   end component;
   attribute BOX_TYPE of PULLUP : component is "BLACK_BOX";
   
   component GND
      port ( G : out   std_logic);
   end component;
   attribute BOX_TYPE of GND : component is "BLACK_BOX";
   
   component COMPM8_MXILINX_top
      port ( A  : in    std_logic_vector (7 downto 0); 
             B  : in    std_logic_vector (7 downto 0); 
             GT : out   std_logic; 
             LT : out   std_logic);
   end component;
   
   component BUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUF : component is "BLACK_BOX";
   
   attribute HU_SET of XLXI_134 : label is "XLXI_134_0";
   attribute HU_SET of XLXI_137 : label is "XLXI_137_1";
begin
   XLXI_29 : IBUF
      port map (I=>XTALIN,
                O=>XLXN_25);
   
   XLXI_31 : OBUF
      port map (I=>XLXN_61,
                O=>XTALOUT1);
   
   XLXI_32 : INV
      port map (I=>XLXN_25,
                O=>XLXN_61);
   
   XLXI_33 : INV
      port map (I=>XLXN_61,
                O=>XLXN_58);
   
   XLXI_59 : OBUF
      port map (I=>XLXN_58,
                O=>XTALOUT2);
   
   XLXI_134 : CJD8CE_MXILINX_top
      port map (C=>XLXN_61,
                CE=>XLXN_176,
                CLR=>XLXN_177,
                Q(7 downto 0)=>Q(7 downto 0));
   
   XLXI_135 : PULLUP
      port map (O=>XLXN_176);
   
   XLXI_136 : GND
      port map (G=>XLXN_177);
   
   XLXI_137 : COMPM8_MXILINX_top
      port map (A(7 downto 0)=>A(7 downto 0),
                B(7 downto 0)=>B(7 downto 0),
                GT=>XLXN_179,
                LT=>XLXN_180);
   
   XLXI_138 : OBUF
      port map (I=>XLXN_179,
                O=>PWMP);
   
   XLXI_139 : OBUF
      port map (I=>XLXN_180,
                O=>PWMN);
   
   XLXI_143 : BUF
      port map (I=>Q(5),
                O=>A(5));
   
   XLXI_144 : BUF
      port map (I=>Q(4),
                O=>A(4));
   
   XLXI_145 : BUF
      port map (I=>Q(3),
                O=>A(3));
   
   XLXI_146 : BUF
      port map (I=>Q(2),
                O=>A(2));
   
   XLXI_148 : BUF
      port map (I=>Q(1),
                O=>A(1));
   
   XLXI_149 : BUF
      port map (I=>Q(0),
                O=>A(0));
   
   XLXI_175 : IBUF
      port map (I=>D5,
                O=>B(5));
   
   XLXI_176 : IBUF
      port map (I=>D4,
                O=>B(4));
   
   XLXI_177 : IBUF
      port map (I=>D3,
                O=>B(3));
   
   XLXI_178 : IBUF
      port map (I=>D2,
                O=>B(2));
   
   XLXI_179 : IBUF
      port map (I=>D1,
                O=>B(1));
   
   XLXI_180 : IBUF
      port map (I=>D0,
                O=>B(0));
end BEHAVIORAL;

Device Used: XC2C64A-7-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  ************************** 

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
14 /64  ( 22%) 42  /224  ( 19%) 28  /160  ( 17%) 8  /64  ( 12%) 11 /33  ( 33%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      10/16     12/40    21/56     0/ 8    1/1*     0/1      0/1      0/1
FB2       0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB3       3/16     15/40    20/56     3/ 9    0/1      0/1      0/1      0/1
FB4       1/16      1/40     1/56     1/ 7    0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    14/64     28/160   42/224    4/33    1/4      0/4      0/4      0/4 

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** 4 Outputs **
Signal              Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
PWMN                14    14    2    FB3_1   29    I/O       O       LVTTL              FAST         
PWMP                10    14    2    FB3_2   28    I/O       O       LVTTL              FAST         
XTALOUT1            1     1     2    FB3_15  18    I/O       O       LVTTL              FAST         
XTALOUT2            1     1     1    FB4_14  14    I/O       O       LVTTL              FAST         

** 7 Inputs **
Signal              Bank Loc     Pin   Pin       Pin     I/O      I/O
Name                             No.   Type      Use     STD      Style
D0                  2    FB1_1   38    I/O       I       LVTTL    KPR
D1                  2    FB1_2   37    I/O       I       LVTTL    KPR
D2                  2    FB1_3   36    I/O       I       LVTTL    KPR
D3                  2    FB1_9   34    GTS/I/O   I       LVTTL    KPR
D4                  2    FB1_10  33    GTS/I/O   I       LVTTL    KPR
D5                  2    FB1_11  32    GTS/I/O   I       LVTTL    KPR
XTALIN              1    FB4_11  12    I/O       I       LVTTL    KPR

******************************  Device Pin Out *****************************
Device : XC2C64A-7-VQ44

   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC2C64A-7-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  

Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 KPR                           
  2 KPR                              24 TDO                           
  3 KPR                              25 GND                           
  4 GND                              26 VCCIO-3.3                     
  5 KPR                              27 KPR                           
  6 KPR                              28 PWMP                          
  7 VCCIO-3.3                        29 PWMN                          
  8 KPR                              30 KPR                           
  9 TDI                              31 KPR                           
 10 TMS                              32 D5                            
 11 TCK                              33 D4                            
 12 XTALIN                           34 D3                            
 13 KPR                              35 VCCAUX                        
 14 XTALOUT2                         36 D2                            
 15 VCC                              37 D1                            
 16 KPR                              38 D0                            
 17 GND                              39 KPR                           
 18 XTALOUT1                         40 KPR                           
 19 KPR                              41 KPR                           
 20 KPR                              42 KPR                           
 21 KPR                              43 KPR                           
 22 KPR                              44 KPR                           
Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin

****************************  Compiler Options  ****************************
Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c64a-7-VQ44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_arith.all;
 
entity top is
    Port ( XTALIN : in  STD_LOGIC;
           XTALOUT1: out STD_LOGIC;
           XTALOUT2: out STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (5 downto 0);
           PWMP : out  STD_LOGIC;
           PWMN : out  STD_LOGIC);
end top;
 
architecture Behavioral of top is
signal COUNT : unsigned ( 5 downto 0 );
signal CLK: STD_LOGIC;
 
begin
CLK <= not XTALIN;
XTALOUT1 <= CLK;
XTALOUT2 <= not CLK;
 
process (CLK)begin
   if CLK'event and CLK='1' then
      COUNT <= COUNT + 1;
   end if;
end process;
 
PWMP <= '0' when std_logic_vector(COUNT) < D else '1';
PWMN <= '0' when std_logic_vector(COUNT) >= D else '1';
 
end Behavioral;

`timescale 1ns / 1ps

module top(
    input XTALIN,
    output XTALOUT1,
    output XTALOUT2,
    output PWMP,
    output PWMN,
    input [5:0] D
    );

wire clk;
reg [5:0] counter;

assign clk = !XTALIN;
assign XTALOUT1 = clk;
assign XTALOUT2 = !clk;

always @(posedge clk)
begin
	counter = counter + 1;
end

wire [5:0] diff = counter-D;
wire sign = diff[5];
assign PWMP = diff?0:1;
assign PWMN = !PWMP;

endmodule