Программирование ARM: решение проблем, FAQ IAR EW ARM: устранение ошибок с отображением регистров Sat, June 24 2017  

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IAR EW ARM: устранение ошибок с отображением регистров Печать
Добавил(а) microsin   

Нашел еще ошибку в IAR - в просмотрщике регистров SSC нет регистров SSC_RC0R и SSC_RC1R, а также нет многих полей в регистрах SSC.

Разобрался, как исправить эту ошибку. Нужно отредактировать текстовый файл ioat91sam7x256.ddf. В IAR версии 4.41A он находится в папке %ProgramFiles% \ IAR Systems \ Embedded Workbench 4.0 Evaluation \ ARM \ config. В IAR версии 5 он находится в папке %ProgramFiles% \ IAR Systems \ Embedded Workbench 5.0 Evaluation \ ARM \ config \ debugger \ Atmel. Это определения всех регистров, которые можно видеть в IDE IAR в режиме отладки.

[Регистры SSC_RC0R и SSC_RC1R]

Я внес следующие изменения в файл DDF:

1. Поправил группу регистров SSC (добавил регистры SSC_RC0R и SSC_RC1R). Было:

group = "SSC", "SSC_CR", "SSC_CMR", "SSC_RCMR", "SSC_RFMR", "SSC_TCMR", "SSC_TFMR", "SSC_RHR", "SSC_THR", "SSC_RSHR", "SSC_TSHR", "SSC_SR", "SSC_IER", "SSC_IDR", "SSC_IMR"

Стало:

group = "SSC", "SSC_CR", "SSC_CMR", "SSC_RCMR", "SSC_RFMR", "SSC_TCMR", "SSC_TFMR", "SSC_RHR", "SSC_THR", "SSC_RSHR", "SSC_TSHR", "SSC_RC0R", "SSC_RC1R", "SSC_SR", "SSC_IER", "SSC_IDR", "SSC_IMR"

2. Добавил описание регистров SSC_RC0R и SSC_RC1R в секции "========== Register definition for SSC peripheral ==========":

sfr = "SSC_RC0R",  "Memory", 0xfffd4038, 4, base=16
sfr = "SSC_RC1R",  "Memory", 0xfffd403C, 4, base=16

3. Добавил определение поля CKG в регистры SSC_RCMR и SSC_TCMR в секции "========== Register definition for SSC peripheral ==========":

sfr = "SSC_RCMR.CKG",  "Memory", 0xfffd4010, 4, base=16, bitRange=6-7
sfr = "SSC_TCMR.CKG",  "Memory", 0xfffd4018, 4, base=16, bitRange=6-7

4. Добавил определение поля STOP в регистр SSC_RCMR в секции "========== Register definition for SSC peripheral ==========":

sfr = "SSC_RCMR.STOP",  "Memory", 0xfffd4010, 4, base=16, bitRange=12

5. Добавил определение полей CP0 и CP1 в регистр SSC_SR в секции "========== Register definition for SSC peripheral ==========":

sfr = "SSC_SR.CP0",  "Memory", 0xfffd4040, 4, base=16, bitRange=8
sfr = "SSC_SR.CP1",  "Memory", 0xfffd4040, 4, base=16, bitRange=9

6. Добавил определение полей CP0 и CP1 в регистр SSC_IMR в секции "========== Register definition for SSC peripheral ==========":

sfr = "SSC_IMR.CP0",  "Memory", 0xfffd404c, 4, base=16, bitRange=8
sfr = "SSC_IMR.CP1",  "Memory", 0xfffd404c, 4, base=16, bitRange=9

Готовый файл ioat91sam7x256.ddf с внесенными изменениями здесь.

[Регистры SPI_CSR]

Изменения, которые я добавил в файл ioat91sam7x256.ddf IAR 4.41A, чтобы корректно отображались регистры SPI0_CSR0, SPI0_CSR1, SPI0_CSR2, SPI0_CSR3 и SPI1_CSR0, SPI1_CSR1, SPI1_CSR2, SPI1_CSR3.

...
sfr = "SPI1_CSR0", 	"Memory", 0xfffe4030, 4, base=16
sfr = "SPI1_CSR0.CPOL", 	"Memory", 0xfffe4030, 4, base=16, bitRange=0
sfr = "SPI1_CSR0.NCPHA", 	"Memory", 0xfffe4030, 4, base=16, bitRange=1
sfr = "SPI1_CSR0.CSAAT", 	"Memory", 0xfffe4030, 4, base=16, bitRange=3
sfr = "SPI1_CSR0.BITS", 	"Memory", 0xfffe4030, 4, base=16, bitRange=4-7
sfr = "SPI1_CSR0.SCBR", 	"Memory", 0xfffe4030, 4, base=16, bitRange=8-15
sfr = "SPI1_CSR0.DLYBS", 	"Memory", 0xfffe4030, 4, base=16, bitRange=16-23
sfr = "SPI1_CSR0.DLYBCT", 	"Memory", 0xfffe4030, 4, base=16, bitRange=24-31
sfr = "SPI1_CSR1", 	"Memory", 0xfffe4034, 4, base=16
sfr = "SPI1_CSR1.CPOL", 	"Memory", 0xfffe4034, 4, base=16, bitRange=0
sfr = "SPI1_CSR1.NCPHA", 	"Memory", 0xfffe4034, 4, base=16, bitRange=1
sfr = "SPI1_CSR1.CSAAT", 	"Memory", 0xfffe4034, 4, base=16, bitRange=3
sfr = "SPI1_CSR1.BITS", 	"Memory", 0xfffe4034, 4, base=16, bitRange=4-7
sfr = "SPI1_CSR1.SCBR", 	"Memory", 0xfffe4034, 4, base=16, bitRange=8-15
sfr = "SPI1_CSR1.DLYBS", 	"Memory", 0xfffe4034, 4, base=16, bitRange=16-23
sfr = "SPI1_CSR1.DLYBCT", 	"Memory", 0xfffe4034, 4, base=16, bitRange=24-31
sfr = "SPI1_CSR2", 	"Memory", 0xfffe4038, 4, base=16
sfr = "SPI1_CSR2.CPOL", 	"Memory", 0xfffe4038, 4, base=16, bitRange=0
sfr = "SPI1_CSR2.NCPHA", 	"Memory", 0xfffe4038, 4, base=16, bitRange=1
sfr = "SPI1_CSR2.CSAAT", 	"Memory", 0xfffe4038, 4, base=16, bitRange=3
sfr = "SPI1_CSR2.BITS", 	"Memory", 0xfffe4038, 4, base=16, bitRange=4-7
sfr = "SPI1_CSR2.SCBR", 	"Memory", 0xfffe4038, 4, base=16, bitRange=8-15
sfr = "SPI1_CSR2.DLYBS", 	"Memory", 0xfffe4038, 4, base=16, bitRange=16-23
sfr = "SPI1_CSR2.DLYBCT", 	"Memory", 0xfffe4038, 4, base=16, bitRange=24-31
sfr = "SPI1_CSR3", 	"Memory", 0xfffe403c, 4, base=16
sfr = "SPI1_CSR3.CPOL", 	"Memory", 0xfffe403c, 4, base=16, bitRange=0
sfr = "SPI1_CSR3.NCPHA", 	"Memory", 0xfffe403c, 4, base=16, bitRange=1
sfr = "SPI1_CSR3.CSAAT", 	"Memory", 0xfffe403c, 4, base=16, bitRange=3
sfr = "SPI1_CSR3.BITS", 	"Memory", 0xfffe403c, 4, base=16, bitRange=4-7
sfr = "SPI1_CSR3.SCBR", 	"Memory", 0xfffe403c, 4, base=16, bitRange=8-15
sfr = "SPI1_CSR3.DLYBS", 	"Memory", 0xfffe403c, 4, base=16, bitRange=16-23
sfr = "SPI1_CSR3.DLYBCT", 	"Memory", 0xfffe403c, 4, base=16, bitRange=24-31
...
sfr = "SPI0_CSR0", 	"Memory", 0xfffe0030, 4, base=16
sfr = "SPI0_CSR0.CPOL", 	"Memory", 0xfffe0030, 4, base=16, bitRange=0
sfr = "SPI0_CSR0.NCPHA", 	"Memory", 0xfffe0030, 4, base=16, bitRange=1
sfr = "SPI0_CSR0.CSAAT", 	"Memory", 0xfffe0030, 4, base=16, bitRange=3
sfr = "SPI0_CSR0.BITS", 	"Memory", 0xfffe0030, 4, base=16, bitRange=4-7
sfr = "SPI0_CSR0.SCBR", 	"Memory", 0xfffe0030, 4, base=16, bitRange=8-15
sfr = "SPI0_CSR0.DLYBS", 	"Memory", 0xfffe0030, 4, base=16, bitRange=16-23
sfr = "SPI0_CSR0.DLYBCT", 	"Memory", 0xfffe0030, 4, base=16, bitRange=24-31
sfr = "SPI0_CSR1", 	"Memory", 0xfffe0034, 4, base=16
sfr = "SPI0_CSR1.CPOL", 	"Memory", 0xfffe0034, 4, base=16, bitRange=0
sfr = "SPI0_CSR1.NCPHA", 	"Memory", 0xfffe0034, 4, base=16, bitRange=1
sfr = "SPI0_CSR1.CSAAT", 	"Memory", 0xfffe0034, 4, base=16, bitRange=3
sfr = "SPI0_CSR1.BITS", 	"Memory", 0xfffe0034, 4, base=16, bitRange=4-7
sfr = "SPI0_CSR1.SCBR", 	"Memory", 0xfffe0034, 4, base=16, bitRange=8-15
sfr = "SPI0_CSR1.DLYBS", 	"Memory", 0xfffe0034, 4, base=16, bitRange=16-23
sfr = "SPI0_CSR1.DLYBCT", 	"Memory", 0xfffe0034, 4, base=16, bitRange=24-31
sfr = "SPI0_CSR2", 	"Memory", 0xfffe0038, 4, base=16
sfr = "SPI0_CSR2.CPOL", 	"Memory", 0xfffe0038, 4, base=16, bitRange=0
sfr = "SPI0_CSR2.NCPHA", 	"Memory", 0xfffe0038, 4, base=16, bitRange=1
sfr = "SPI0_CSR2.CSAAT", 	"Memory", 0xfffe0038, 4, base=16, bitRange=3
sfr = "SPI0_CSR2.BITS", 	"Memory", 0xfffe0038, 4, base=16, bitRange=4-7
sfr = "SPI0_CSR2.SCBR", 	"Memory", 0xfffe0038, 4, base=16, bitRange=8-15
sfr = "SPI0_CSR2.DLYBS", 	"Memory", 0xfffe0038, 4, base=16, bitRange=16-23
sfr = "SPI0_CSR2.DLYBCT", 	"Memory", 0xfffe0038, 4, base=16, bitRange=24-31
sfr = "SPI0_CSR3", 	"Memory", 0xfffe003c, 4, base=16
sfr = "SPI0_CSR3.CPOL", 	"Memory", 0xfffe003c, 4, base=16, bitRange=0
sfr = "SPI0_CSR3.NCPHA", 	"Memory", 0xfffe003c, 4, base=16, bitRange=1
sfr = "SPI0_CSR3.CSAAT", 	"Memory", 0xfffe003c, 4, base=16, bitRange=3
sfr = "SPI0_CSR3.BITS", 	"Memory", 0xfffe003c, 4, base=16, bitRange=4-7
sfr = "SPI0_CSR3.SCBR", 	"Memory", 0xfffe003c, 4, base=16, bitRange=8-15
sfr = "SPI0_CSR3.DLYBS", 	"Memory", 0xfffe003c, 4, base=16, bitRange=16-23
sfr = "SPI0_CSR3.DLYBCT", 	"Memory", 0xfffe003c, 4, base=16, bitRange=24-31
...
group = "SPI0", "SPI0_CR", ..., "SPI0_IMR", "SPI0_CSR0" "SPI0_CSR1" "SPI0_CSR2" "SPI0_CSR3"
...
group = "SPI0", "SPI0_CR", ..., "SPI0_IMR", "SPI0_CSR0" "SPI0_CSR1" "SPI0_CSR2" "SPI0_CSR3"
...

 

 

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